Modern computer systems and data processing systems make high demands on the data memories used therein. The memories should be capable of providing extensive data within a short access time. Fast data memories meeting these demands are data memories with electronic integrated memory devices such as, for example, so-called DRAM (Dynamic Random Access Memory) devices.
Often, however, memory capacities are demanded which cannot be met by a single device. A number of integrated memory devices are therefore embedded in a high-capacity memory system in a conventional manner. The individual integrated memory device should therefore cooperate with memory controllers and/or other memory devices in order to ensure interference-free and time-efficient coordination of the data flow.
In conventional memory systems comprising a number of integrated memory devices or memory devices, a read request, for example, is delivered to all memory devices, to a group of memory devices or to an individual memory device, where the corresponding memory device then delivers the requested data after a so-called latency period after receiving the read request. The latency period is thus defined here in the sense of the time interval from the delivery of a read request to the reception of the requested data. The memory systems comprise a number of individual memory devices which are produced in high numbers with the aid of complex and highly developed production processes.
In spite of the high and optimized reproducibility of established production processes, it is impossible to produce identical devices. Instead, the individual devices are subject to process-related variances which are mainly noticeable with regard to a latency period varying from device to device.
Furthermore, fluctuations in the supply voltage and the environmental temperature also lead to a change in the latency period during the operation. The variances are also collectively referred to as PVT (Process Voltage Temperature) variances. The time interval between the request and receiving the data thus varies and cannot be adjusted precisely.
The varying latency period of conventional memory devices leads to certain restrictions with regard to the time efficiency in the interaction of a number of memory devices. for example, to increase the number of integrated memory devices in a memory system—and thus also the total memory capacity—whilst simultaneously minimizing access time, the individual integrated memory device should be capable of reliably providing the requested data after a well defined access time which is constant over the entire operation. Additionally, if a number of memory devices use a common data bus for outputting the data, as for example in a cascaded circuit, it becomes necessary that the individual memory device inserts the data into a data stream at a well defined and determinable time. Otherwise, collisions arise when a memory device outputs data at a time at which data signals are already present at the location of the signal entry. Furthermore, too generous a waiting time between two successive read requests leads to under-utilization of the signal paths.